This research proposal presents a comprehensive hardware-software co-design framework for analog in-memory Bayesian neural network inference at the edge. The approach leverages memristor crossbar arrays and their inherent device stochasticity as a natural source of randomness for Bayesian inference, eliminating the need for external random number generators. The framework integrates novel hardware-aware variational inference algorithms with a joint optimization methodology that co-tunes network architecture, hardware parameters, and inference procedures. Projected results demonstrate 3.8×–9.6× improvements in total efficiency and 2.2×–5.6× in power efficiency compared to SRAM-based baselines while maintaining calibration quality comparable to software-based BNN implementations.
Key findings
Memristor device stochasticity serves as an intrinsic randomness source for Bayesian inference, eliminating external RNG requirements.
Hardware-aware variational inference algorithms account for analog non-idealities including conductance drift and programming noise.
Joint optimization of network architecture, hardware parameters, and inference procedures maximizes overall system efficiency.
Projected improvements of 3.8×–9.6× in total efficiency (GOPS/W/mm²) over SRAM-based digital implementations.
Maintains calibration quality comparable to software-based BNNs while achieving orders-of-magnitude energy efficiency gains.
Limitations & open questions
Algorithm-hardware mismatch due to analog device variations and limited precision (typically 4-6 bits).
Experimental validation remains pending as this is a research proposal rather than completed work.
Systematic methods for harnessing memristor stochasticity for probabilistic computing remain underdeveloped.