This research proposal presents a comprehensive in-memory computing (IMC) architecture for on-chip neural spike sorting using resistive RAM (RRAM) crossbar arrays. The proposed system integrates analog front-end circuits with RRAM-based matrix-vector multiplication to perform spike detection, feature extraction, and clustering entirely within memory. The modular design supports 64 to 1024 channels and projects 50×-100× energy efficiency improvements and sub-millisecond latency compared to conventional digital implementations.
Key findings
Novel hybrid IMC architecture combining RRAM crossbar arrays with specialized analog spike detection circuits enables end-to-end on-chip processing.
Adaptive clustering algorithm based on locally competitive sparse coding is optimized for in-memory implementation.
Modular framework demonstrates scalability from 64 to 1024 channels with predictable performance characteristics.
Benchmarking projects 50× to 100× energy efficiency improvements and 30× area efficiency gains versus FPGA-based solutions.
Achieves sub-millisecond latency per spike, addressing real-time requirements for closed-loop brain-computer interfaces.
Limitations & open questions
RRAM device non-idealities and variability pose challenges for analog computation accuracy requiring compensation mechanisms.
Signal drift over extended recording periods necessitates robust real-time adaptability algorithms.
Current proposal relies on simulation-based benchmarking; physical chip validation is required to confirm projected metrics.